1. Field of the Invention
The present invention relates to a microprogram control system, and particularly to a microprogram control system in a data processing unit employing a pipeline control system, wherein flexibility is imparted to the system by reading microinstructions and suppressing a hardware control mode to execute processings with microinstructions corresponding to each flow when executing an instruction which results in processing several flows.
2. Description of the Related Art
As shown in FIG. 1, for example, prefetched instructions are executed in each stages D, A, T, B, E and W by a pipeline processor. In FIG. 1, 1 is an instruction word register for an instruction word. 2 is a control storage or memory storing microinstructions. 3 to 7 are microinstruction field registers which issue instructions for processing to the hardware corresponding to stages D to W. 8 is a general purpose register group. 9 is a base register. 10 is an index register. 11 is a displacement register. 12 is an address calculator or three input adder. 13 is a logical address register. 14 is a TLB (Address Translation Buffer). 15 is an address buffer. 16 is a buffer memory. 17 is an operand register. 18 to 20 are operand buffer registers. 21 is an operand register. 22 is an operation unit such as an adder. 23 is a result register. The general purpose register group 8 is a register group to be used in the three stages D, B and W.
When an instruction 1 is supplied to the pipeline indicated in FIG. 1, a microinstruction required for executing the pertinent instruction 1 is read and loaded into the register 3 in stage D (decode). Simultaneously, a value is loaded into the registers 9, 10 and 11 to calculate the address for the operand (Opr 2 in the figure) which is required for executing the pertinent instruction 1. The address of the operand Opr 2 is calculated by the calculator 12 in stage A (address) and the result is loaded into the logical address register 13. The TLB 14 and buffer memory 16 are indexed through the stages T (translate) and B (buffer access) and a value of the operand is loaded into the register 17. At this time, a value of operand Opr 1 is also loaded into the register 21. At this point, the specified operation is carried out by operation unit 22 in the stage E (execution) and the operation result is loaded into the general purpose register 8 in the stage W (write).
The pipeline control is conducted as explained above and the processings for each stage advances in such a way that the microinstructions are read from the control memory 2 shown in the figure and these instructions are executed sequentially. On the one hand, when of executing a given instruction 1, the necessary processings are sometimes not completed by only the processing flow executed along the pipeline processing stages from stage D to stage W in FIG. 1 (called the processing flow). In general, a plurality of processing flows are required for execution of some instructions and the respective processing flows are desired to be completely executed by microinstructions. In such a case, the bit groups of microinstructions corresponding to one flow of processing read from the control memory 2 are forced to correspond to the controls for respective stages of the pipeline and thereby the respective corresponding bit groups instruct the processing in respective stages from the registers 3, 4, 5, 6, 7 shown in FIG. 1.
As explained above, instructions have been developed for a plurality of flows and processing has been conducted by reading microinstructions corresponding to respective flows from the control memory 2. But, there is a restriction in the time (a minimum available or necessary) for accessing the control memory 2 and as a result the controls in stage D of each flow has been performed by hardware and it has been difficult to employ a control method using microprograms.
Accordingly, the hardware is large in size and when modifications of functions at stage D are required, the hardware must be modified. Thereby, although it is a data processing unit executing on the basis of microprogram control system, it does not have sufficient flexibility in the microprogram control for the modification of functions. Therefore, a system which can realize the microprogram control in all stages is desired.
Namely, the microprogram control system of the prior art which controls a data processing unit for pipeline processing takes a longer time for reading control memory and delay for timing for control of the first stage (stage D) of pipeline are necessary. As a result, this stage has been controlled by a hardware decoder or a dummy cycle has been inserted in the cycle clock in order to provide sufficient time to read the control memory.
The control using hardware, however, has a disadvantage in that it is difficult to realize flexible and sophisticated control and the method of inserting the dummy cycle is also followed by a disadvantage in that the dummy cycle appears between the processing times for the instructions, thereby lowering processing speed.